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INTEGRATED CIRCUITS
74ALVT16841 2.5V/3.3V ALVT 20-bit bus interface latch (3-State)
Product specification Supersedes data of 1996 Aug 28 IC23 Data Handbook 1998 Feb 13
Philips Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
FEATURES
* High speed parallel latches * 5V I/O Compatible * Live insertion/extraction permitted * Extra data width for wide address/data paths or buses carrying * Power-up 3-State * Power-up reset * Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors parity
DESCRIPTION
The 74ALVT16841 Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. It is designed for VCC operation at 2.5V or 3.3V with I/O compatibility to 5V. The 74ALVT16841 consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state.
* Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * Bus-hold data inputs eliminate the need for external pull-up * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model resistors to hold unused inputs
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COut ICCZ PARAMETER Propagation delay nDx to nQx Input capacitance DIR, OE Output pin capacitance Total supply current CL = 50pF VI = 0V or VCC VI/O = 0V or VCC Outputs disabled CONDITIONS Tamb = 25C TYPICAL UNIT 2.5V 1.8 2.1 3 9 40 3.3V 1.5 1.7 3 9 70 ns pF pF A
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ALVT16841 DL 74ALVT16841 DGG NORTH AMERICA AV16841 DL AV16841 DGG DWG NUMBER SOT371-1 SOT364-1
1998 Feb 13
2
853-1868 18961
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
LOGIC SYMBOL
55 54 52 51 49 48 47 45 44 43
PIN CONFIGURATION
1OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1LE 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5 1D6 GND 1D7 1D8 1D9 2D0 2D1 2D2 GND 2D3 2D4 2D5 VCC 2D6 2D7 GND 2D8 2D9 2LE
1D0 1D1 1D2 1D3 1D4 1D5 1D6 56 1 1LE 1OE
1D7 1D8
1D9
1Q0 1Q1 GND 1Q2 1Q3
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2 42
3 41
5 40
6 38
8 37
9 36
10 34
12 33
13 31
14 30
VCC 1Q4 1Q5
2D0 2D1 2D2 2D3 2D4 2D5 2D6 29 28 2LE 2OE
2D7 2D8
2D9
1Q6 GND 1Q7 1Q8
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 1Q9 2Q0 15 16 17 19 20 21 23 24 26 27 2Q1
SH00023
2Q2 GND
LOGIC SYMBOL (IEEE/IEC)
1 56 28 29 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 3D 4 EN2 C1 EN4 C3 1D 2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27
2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2Q9 2OE
SA00076
SA00077
1998 Feb 13
3
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
PIN DESCRIPTION
PIN NUMBER 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1, 28 56, 29 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL 1D0 - 1D9 2D0 - 2D9 FUNCTION
FUNCTION TABLE
INPUTS nOE Data inputs L L L L Data outputs H nLE H H X nDx L H l h X OUTPUTS nQ0 - nQ9 L H L H Z OPERATING MODE
Transparent Latched High impedance
1Q0 - 1Q9 2Q0 - 2Q9
1OE, 2OE 1LE, 2LE GND VCC
Output enable inputs (active-Low) Latch enable inputs (active rising edge) Ground (0V) Positive supply voltage
L L X NC Hold H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE transition = High-to-Low LE transition NC= No change X = Don't care Z = High impedance "off" state
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9
D
D
D
D
D
D
D
D
D
D
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
nLE
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9
SH00024
1998 Feb 13
4
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 DC output current Output in High state Storage temperature range -64 -65 to 150 C VO < 0 Output in Off or High state Output in Low state VI < 0 CONDITIONS RATING -0.5 to +4.6 -50 -1.2 to +7.0 -50 -0.5 to +7.0 128 mA UNIT V mA V mA V
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%; f 1kHz Input transition rise or fall rate; Outputs enabled Operating free-air temperature range -40 PARAMETER 2.5V RANGE LIMITS MIN 2.3 0 1.7 0.7 -8 8 24 10 +85 -40 MAX 2.7 5.5 3.3V RANGE LIMITS MIN 3.0 0 2.0 0.8 -32 32 64 10 +85 MAX 3.6 5.5 UNIT V V V V mA mA ns/V C
1998 Feb 13
5
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
DC ELECTRICAL CHARACTERISTICS (3.3V "0.3V RANGE)
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIK VOH Input clamp voltage High-level out ut voltage output VCC = 3.0V; IIK = -18mA VCC = 3 0 to 3 6V; IOH = -100A 3.0 3.6V; VCC = 3.0V; IOH = -32mA VCC = 3.0V; IOL = 100A VOL Low-level out ut voltage output VCC = 3.0V; IOL = 16mA VCC = 3.0V; IOL = 32mA VCC = 3.0V; IOL = 64mA VRST Power-up output low voltage6 VCC = 3.6V; IO = 1mA; VI = VCC or GND VCC = 3.6V; VI = VCC or GND II Input leakage current In ut VCC = 0 or 3.6V; VI = 5.5V VCC = 3.6V; VI = VCC VCC = 3.6V; VI = 0V IOFF IHOLD Off current Bus Hold current Data inputs7 Current into an output in the High state when VO > VCC Power up/down 3-State output current3 3-State output High current 3-State output Low current VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V VCC = 3V; VI = 2.0V VCC = 0V to 3.6V; VCC = 3.6V VO = 5.5V; VCC = 3.0V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC OE/OE = Don't care VCC = 3.6V; VO = 3.0V; VI = VIL or VIH VCC = 3.6V; VO = 0.5V; VI = VIL or VIH VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 05 Additional supply current per input pin2 VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND 75 -75 500 10 1 0.5 0.5 0.07 3.2 0.07 0.04 125 100 5 -5 0.1 7 0.1 0.4 mA mA A A A A Data pins4 ins Control pins 0.1 0.1 0.5 0.1 0.1 130 -140 A VCC-0 2 -0.2 2.0 TYP1 -0.85 VCC 2.3 0.07 0.25 0.3 0.4 0.2 0.4 0.5 0.55 0.55 1 10 1 -5 100 A A V V MAX -1.2 V V UNIT
IEX IPU/PD IOZH IOZL ICCH ICCL ICCZ ICC
NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V 0.3V a transition time of 100sec is permitted. This parameter is valid for Tamb = 25C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 13
6
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
AC CHARACTERISTICS (3.3V "0.3V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay nDx to nQx Propagation delay nLE to nQx Output enable time to High and Low level Output disable time from High and Low level 2 1 4 5 4 5 0.5 0.5 1.0 1.5 1.0 0.5 1.5 1.5 Tamb = -40 to +85oC VCC = +3.3V 0.3V TYP 1.5 1.7 2.1 3.4 2.3 1.3 3.2 2.8 MAX 2.5 2.7 3.2 5.5 3.6 2.3 4.9 4.3 ns ns ns ns UNIT
NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC SETUP REQUIREMENTS (3.3V "0.3V RANGE)
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = -40 to +85oC VCC = +3.3V 0.3V Min ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low nDx to nLE Hold time, High or Low nDx to nLE nLE pulse width High 3 3 1 1.0 1.0 1.2 1.2 1.5 Typ 0 0 0.1 0.3 ns ns ns UNIT
1998 Feb 13
7
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
DC ELECTRICAL CHARACTERISTICS (2.5V "0.2V RANGE)
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C MIN VIK VOH Input clamp voltage High-level out ut voltage output VCC = 2.3V; IIK = -18mA VCC = 2.3 to 3.6V; IOH = -100A VCC = 2.3V; IOH = -8mA VCC = 2.3V; IOL = 100A VOL Low-level output voltage VCC = 2.3V; IOL = 24mA VCC = 2.3V; IOL = 8mA VRST Power-up output low voltage7 VCC = 2.7V; IO = 1mA; VI = VCC or GND VCC = 2.7V; VI = VCC or GND II In ut Input leakage current VCC = 0 or 2.7V; VI = 5.5V VCC = 2.7V; VI = VCC VCC = 2.7V; VI = 0 IOFF IHOLD Off current Bus Hold current Data inputs6 IEX IPU/PD IOZH IOZL ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Current into an output in the High state when VO > VCC Power up/down 3-State output current3 3-State output High current 3-State output Low current VCC = 0V; VI or VO = 0 to 4.5V VCC = 2.3V; VI = 0.7V VCC = 2.3V; VI = 1.7V VO = 5.5V; VCC = 2.3V VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don't care VCC = 2.7V; VO = 2.3V; VI = VIL or VIH VCC = 2.7V; VO = 0.5V; VI = VIL or VIH VCC = 2.7V; Outputs High, VI = GND or VCC, IO = 0 VCC = 2.7V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 2.7V; Outputs Disabled; VI = GND or VCC, IO = VCC = 2.3V to 2.7V; One input at VCC-0.6V, Other inputs at VCC or GND 05 Data pins4 ins Control pins 0.1 0.1 0.1 0.1 0.1 90 -10 10 1 0.5 0.5 0.04 2.3 0.04 0.04 125 "100 5 -5 0.1 4.5 0.1 0.4 mA mA VCC-0.2 1.8 TYP1 -0.85 VCC 2.1 0.07 0.3 0.2 0.5 0.4 0.55 1 10 1 -5 "100 A A A A A A A V V MAX -1.2 V V UNIT
NOTES: 1. All typical values are at VCC = 2.5V and Tamb = 25C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 2.5V 0.2V a transition time of 100sec is permitted. This parameter is valid for Tamb = 25C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. Not guaranteed. 7. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
1998 Feb 13
8
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
AC CHARACTERISTICS (2.5V "0.2V RANGE)
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500; Tamb = -40C to +85C. LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPZH tPZL Propagation delay nDx to nQx Propagation delay nLE to nQx Output enable time to High and Low level 2 1 4 5 4 5 0.5 0.5 1.0 2.0 1.5 0.5 1.5 1.0 Tamb = -40 to +85oC VCC = +2.5V 0.2V TYP 1.8 2.1 2.7 4.2 3.0 1.8 3.1 2.4 MAX 3.0 3.6 4.3 6.5 4.0 3.2 4.5 3.8 ns ns ns ns UNIT
tPHZ Output disable time tPLZ from High and Low level NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25C.
AC SETUP REQUIREMENTS (2.5V "0.2V RANGE)
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = -40 to +85oC VCC = +2.5V 0.2V Min ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low nDx to nLE Hold time, High or Low nDx to nLE nLE pulse width High 3 3 1 0.5 1.5 1.8 2.0 1.5 Typ 0 0.2 0 0.8 ns ns ns UNIT
1998 Feb 13
9
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
AC WAVEFORMS
VM = 1.5V at VCC w 3.0V; VM = VCC/2 at VCC v 2.7V VX = VOL + 0.3V at VCC w 3.0V; VX = VOL + 0.15V at VCC v 2.7V VY = VOH - 0.3V at VCC w 3.0V; VY = VOH - 0.15V at VCC v 2.7V
3.0V or VCC whichever is less 0V tw(H) tPHL nQx VM tPLH VOH VM VOL nQx VM tPZH tPHZ VOH VY 0V 3.0V or VCC whichever is less 0V
nOE VM VM
nLE
VM
VM
VM
SH00007
SA00078
Waveform 1. Propagation Delay, Latch Enable Input to Output, and Enable Pulse Width
nOE 3.0V or VCC whichever is less 0V tPLH tPHL 3.0V or VCC whichever is less 0V nQx
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
VM tPZL
VM tPLZ
3.0V or VCC whichever is less 0V
nDx INPUT
VM
VM
3.0V or VCC VM VX VOL 0V
nQx OUTPUT
VM
VM
SH00008
SA00079
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
Waveform 2. Propagation Delay for Data to Outputs
nDx
VM
VM
VM
VM
3.0V or VCC whichever is less
nLE
1998 Feb 13
EEEEEEEEE EEE E EEEEEEEEE EEE E
ts(H) th(H) ts(L) th(L) VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
0V 3.0V or VCC whichever is less
0V
SA00080
Waveform 3. Data Setup and Hold Times
10
Philips Semiconductors
Product specification
2.5V/3.3V 20-bit bus interface latch (3-State)
74ALVT16841
TEST CIRCUIT AND WAVEFORM
6.0V or VCC x 2 90%
VCC
tW VM 10% tTHL (tF) 10% VM
90%
VIN
Open
VIN PULSE GENERATOR RT D.U.T. CL RL VOUT RL
GND
NEGATIVE PULSE
0V tTLH (tR) tTHL (tF) VIN VM 10% tW 0V
tTLH (tR) 90% 90% POSITIVE PULSE 10%
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ/tPZL tPLH/tPHL tPHZ/tPZH SWITCH 6V or VCC x 2 Open GND INPUT PULSE REQUIREMENTS FAMILY Amplitude Rep. Rate tW 500ns tR tF
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
74ALVT16
3.0V or VCC whichever v10MHz is less
v2.5ns v2.5ns
SW00025
1998 Feb 13
11
Philips Semiconductors
Product specification
2.5V/3.3V ALVT 20-bit bus interface latch (3-State)
74ALVT16841
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1998 Feb 13
12
Philips Semiconductors
Product specification
2.5V/3.3V ALVT 20-bit bus interface latch (3-State)
74ALVT16841
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Feb 13
13
Philips Semiconductors
Product specification
2.5V/3.3V ALVT 20-bit bus interface latch (3-State)
74ALVT16841
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03578
Philips Semiconductors
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